This invention pertains to the field of organic thin film field effect transistors (TFT), in particular to flat panel liquid crystal displays using such transistors.
Thin film field effect transistors (TFT) used in liquid crystal display (LCD) applications typically use amorphous silicon (a-Si:H) as the semiconductor and silicon oxide and/or silicon nitride as the gate insulator. Recent developments in materials have led to the exploration of organic oligomers such as hexathiophene and derivatives, and organic molecules such as pentacene (G. Horowitz, D. Fichou, X. Peng, Z. Xu, F. Garnier, Solid State Commun. Volume 72, pg. 381, 1989; F. Garnier, G. Horowitz, D. Fichou, U.S. Pat. No. 5,347,144) as potential replacements for amorphous silicon as the semiconductor in thin-film field-effect transistors.
The highest field effect mobility in thiophene-oligomer-based TFT""s is usually about 0.06 cm2 Vxe2x88x921 secxe2x88x921 (F. Garnier, R. Hajlaoui, A. Yassar, P. Srivastava, Science, Volume 265, pg. 1684, 1994), which is substantially lower than the mobility of standard a-Si:H TFT""s. Only in the case that the organic insulator cyanoethylpullulane was used, was a higher field effect mobility measured (0.4 cm2 Vxe2x88x921 secxe2x88x921, F. Garnier, G. Horowitz, D. Fichou, U.S. Pat. No. 5,347,144). However, that insulator exhibits some undesirable characteristics such as inferior dielectric strength, mobile charges, (G. Horowitz, F. Deloffre, F. Garnier, R. Hajlaoui, M. Hmyene, A. Yassar, Synthetic Metals, Volume 54, pg 435, 1993) and sensitivity to humidity. Hence it is not suitable for use as a gate insulator in the fabrication of practical TFT devices. Field effect mobility up to 0.6 cm2 Vxe2x88x921 secxe2x88x921 has recently been achieved in pentacene based TFT""s with SiO2 as the gate insulator (Y. Y. Lin, D. J. Gundlach, T. N. Jackson, 54th Annual Device Research Conference Digest, 1996 pg. 80), making them potential candidates for such applications. Major drawbacks of these pentacene-based organic TFT""s are high threshold voltage, high operating voltages required to achieve high mobility and simultaneously produce high current modulation (typically about 100 V when 0.4 xcexcm thick SiO2 insulator is used), and high sub-threshold slope, S, which is approximately 14 V per decade of current modulation (Y. Y. Lin, D. J. Gundlach, T. N. Jackson, 54th Annual Device Research Conference Digest, 1996, pg. 80) as compared to about 0.3 V per decade of current modulation achieved in a-Si:H based TFT""s (C.-Y. Chen, J. Kanicki, 54th Annual Device Research Conference Digest, 1996, pg. 68). Reducing the thickness of the gate insulator would improve the above mentioned characteristics but there is a limit to the decrease of the insulator thickness, which is imposed by ease of manufacturing and reliability issues. For example in the current generation of TFT LCD devices the thickness of the TFT gate insulator is typically 0.4 xcexcm.
The electrical characteristics of TFT""s having pentacene as the semiconductor, a heavily doped Si-wafer as the gate electrode, thermally grown SiO2 on the surface of the Si-wafer as the gate insulator, and Au source and drain electrodes, are adequately modeled by standard field effect transistor equations (S. M. Sze xe2x80x9cPhysics of Semiconductor Devicesxe2x80x9d, Wiley, N.Y., 1981, pg. 442), as shown previously (G. Horowitz, D. Fichou, X. Peng, Z. Xu, F. Garnier, Solid State Commun. Volume 72, pg. 381, 1989; C. D. Dimitrakopoulos, A. R. Brown, A. Pomp, J. Appl. Phys. Volume 80, pg. 2501, 1996). The pentacene used in these devices behaves as a p-type semiconductor. FIG. 1, cited from Y. Y. Lin, D. J. Gundlach, T. N. Jackson, 54th Annual Device Research Conference Digest, 1996, pg. 80, shows the dependence of the current flowing between the source and drain electrodes (ID) on the voltage applied to the drain electrode (VD), at discrete voltages applied to the gate electrode (VG). When the gate electrode is biased negatively with respect to the grounded source electrode, pentacene-based TFT""s operate in the accumulation mode and the accumulated carriers are holes. At low VD, ID increases linearly with VD (linear region) and is approximately given by the equation:                               I          D                =                                            W              ⁢                              xe2x80x83                            ⁢                              C                i                                      L                    ⁢          μ          ⁢                      xe2x80x83                    ⁢                      (                                          V                G                            -                              V                T                            -                                                V                  D                                2                                      )                    ⁢                      xe2x80x83                    ⁢                      V            D                                              (        1        )            
where L is the channel length, W is the channel width, Ci is the capacitance per unit area of the insulating layer, VT is a threshold voltage, and xcexc is the field effect mobility. xcexc can be calculated in the linear region from the transconductance:                                           g            m                    =                                                    (                                                      ∂                                          I                      D                                                                            ∂                                          V                      G                                                                      )                                                              V                  D                                =                const                                      =                                                            W                  ⁢                                      xe2x80x83                                    ⁢                                      C                    i                                                  L                            ⁢              μ              ⁢                              xe2x80x83                            ⁢                              V                D                                                    ,                            (        2        )            
by plotting ID vs. VG at a constant low VD and equating the value of the slope of this plot to gm.
When the drain electrode is more negatively biased than the gate electrode (i.e. xe2x88x92VDxe2x89xa7xe2x88x92VG), with the source electrode being grounded (i.e. Vs=0), the current flowing between source and drain electrodes (ID) tends to saturate (does not increase any further) due to the pinch-off in the accumulation layer (saturation region), and is modeled by the equation:                               I          D                =                                            W              ⁢                              xe2x80x83                            ⁢                              C                i                                                    2              ⁢              L                                ⁢          μ          ⁢                      xe2x80x83                    ⁢                                                    (                                                      V                    G                                    -                                      V                    T                                                  )                            2                        .                                              (        3        )            
FIG. 2 a shows the dependence of ID on VG in saturation (Y. Y. Lin, D. J. Gundlach, T. N. Jackson, 54th Annual Device Research Conference Digest, 1996, pg. 80). The field effect mobility can be calculated from the slope of the {square root over (|ID+L |)} vs. VG plot. FIG. 2b shows a plot of the square root of ID vs VG. A mobility of 0.62 cm2 Vxe2x88x921 secxe2x88x921 can be calculated from this plot. The sub-threshold slope, S, is approximately 14 volts per decade of current modulation (Y. Y. Lin, D. J. Gundlach, T. N. Jackson, 54th Annual Device Research Conference Digest, 1996, pg. 80).
It is an object of this invention is to demonstrate TFT structures that overcome the need to use high operating voltages in order to achieve the desirable combination of high field effect mobility, low threshold voltage, low sub-threshold slope, and high current modulation, without having to reduce the thickness of the insulator. Such structures contain an inorganic high dielectric constant gate insulator layer (for example, barium strontium titanate) in combination with an organic semiconductor (for example, pentacene).
It is another object of this invention to produce organic TFT structures wherein the high dielectric constant gate insulator is deposited and processed at temperatures compatible with glass and plastic substrates (150 to 400xc2x0 C.), which are substantially lower than the processing temperatures of these materials when they are used for memory applications (up to 650xc2x0 C.).
The proposed TFT structures make use of a high dielectric constant thin film gate insulator, an organic semiconductor such as pentacene, and a metal, conducting polymer, highly doped high conductivity material or a combination thereof as the gate, source, and drain electrodes.
There are many candidate materials with high dielectric constant that can be used as gate insulator layers in the above structures, including but not restricted to Ta2O5, Y2O3, TiO2, and the family of ferroelectric insulators, including but not restricted to PbZrxTi1xe2x88x92xO3 (PZT), Bi4Ti3O12, BaMgF4, barium zirconate titanate (BZT) and BaxSr1xe2x88x92xTiO3 (BST). These materials have been studied and used in the past in combination with inorganic semiconductors mainly for memory device applications (P. Balk, Advanced Materials, Volume 7, pg. 703, 1995 and references therein) but never in combination with organic semiconductors. Typically these insulators are annealed at 600xc2x0 C. or higher to achieve dielectric constant (xcex5) values exceeding 150.
In general the proposed structure uses an inorganic, high dielectric constant gate insulator in combination with an organic semiconductor (e.g. pentacene) in a TFT structure. The high xcex5 insulator is annealed at 400xc2x0 C. to achieve an xcex5xe2x89xa715, which makes possible the use of glass or plastic substrates. If a high dielectric constant organic insulator was available (xcex5xe2x89xa715) which also fulfilled other requirements, such as environmental stability, high breakdown voltage, good film-forming capability, absence of mobile charges, it could also be used instead of the previously mentioned inorganic insulators for the proposed structures.
A typical sequence used in the fabrication of the proposed TFT structures includes the following steps:
preparation of the gate electrode, which can be either the substrate itself, in such case being heavily doped Si, or a patterned metal (or conducting polymer or other conductive material) gate electrode deposited and patterned on a substrate;
deposition of the high dielectric constant gate insulator on top of the gate electrode by one of various processes including but not restricted to sol gel spin coating and baking, sputtering, chemical vapor deposition (CVD), laser ablative deposition, and physical vapor deposition;
optionally annealing the films at a suitable temperature in the range of 150 to 400xc2x0 C. to improve the film quality and enhance the dielectric constant;
deposition of the organic semiconductor on top of the gate insulator by one of various processes including but not restricted to vapor deposition, spin-coating from solution or self assembly of layers from solution;
fabrication of the electrically conducting source and drain electrodes on top of the organic semiconductor;
and optionally applying a passivation coating of an insulator by chemical vapor deposition (CVD), physical vapor deposition or spin coating and curing.
The sequence of the steps comprising the deposition of the organic semiconductor and the fabrication of the source and drain electrodes could be reversed to allow process compatibility and ease of fabrication.